A Sustainable Autonomic Architecture for Organically Reconfigurable Computing Systems

A Sustainable Autonomic Architecture for Organically Reconfigurable Computing System based on SRAM Field Programmable Gate Arrays (FPGAs) is proposed, modeled analytically, simulated, prototyped, and measured. Low-level organic elements are analyzed and designed to achieve novel self-monitoring, self-diagnosis, and self-repair organic properties. The prototype of a 2-D spatial gradient Sobel video edge-detection organic system use-case developed on a XC4VSX35 Xilinx Virtex-4 Video Starter Kit is presented. Experimental results demonstrate the applicability of the proposed architecture and provide the infrastructure to quantify the performance and overcome fault-handling limitations. Dynamic online autonomous functionality restoration after a malfunction or functionality shift due to changing requirements is achieved at a fine granularity by exploiting dynamic Partial Reconfiguration (PR) techniques. A Genetic Algorithm (GA)-based hardware/software platform for intrinsic evolvable hardware is designed and evaluated for digital circuit repair using a variety of well-accepted benchmarks. Dynamic bitstream compilation for enhanced mutation and crossover operators is achieved by directly manipulating the bitstream using a layered toolset. Experimental results on the edge-detector organic system prototype have shown complete organic online refurbishment after a hard fault. In contrast to previous toolsets requiring many milliseconds or seconds, an average of 0.47 microseconds is required to perform the genetic mutation, 4.2 microseconds to perform the single point conventional crossover, 3.1 microseconds to perform Partial Match Crossover (PMX) as well as Order Crossover (OX), 2.8 microseconds to perform Cycle Crossover (CX), and 1.1 milliseconds for one input pattern intrinsic evaluation. These represent a performance advantage of three orders of magnitude over the JBITS software framework and more than seven orders of magnitude over the Xilinx design flow. Combinatorial Group Testing (CGT) technique was combined with the conventional GA in what is called CGT-pruned GA to reduce repair time and increase system availability. Results have shown up to 37.6% convergence advantage using the pruned technique. Lastly, a quantitative stochastic sustainability model for reparable systems is formulated to evaluate the Sustainability of FPGA-based reparable systems. This model computes at design-time the resources required for refurbishment to meet mission availability and lifetime requirements in a given fault-susceptible missions. By applying this model to MCNC benchmark circuits and the Sobel Edge-Detector in a realistic space mission use-case on Xilinx Virtex-4 FPGA, we demonstrate a comprehensive model encompassing the inter-relationships between system sustainability and fault rates, utilized, and redundant hardware resources, repair policy parameters and decaying reparability

Intrinsic Evolvable Hardware Platform For Digital Circuit Design And Repair Using Genetic Algorithms

A hardware/software platform for intrinsic evolvable hardware is designed and evaluated for digital circuit design and repair on Xilinx Field Programmable Gate Arrays (FPGAs). Dynamic bitstream compilation for mutation and crossover operators is achieved by directly manipulating the bitstream using a layered framework. Experimental results on a case study have shown that benchmark circuit evolution from an unseeded initial population, as well as a complete recovery of a stuck-at fault is achievable using this platform. An average of 0.47 μs is required to perform the genetic mutation, 4.2 μs to perform the single point conventional crossover, 3.1 μs to perform Partial Match Crossover (PMX) as well as Order Crossover (OX), 2.8 μs to perform Cycle Crossover (CX), and 1.1 ms for one input pattern intrinsic evaluation. These represent a performance advantage of three orders of magnitude over the JBITS software framework and more than seven orders of magnitude over the Xilinx design tool driven flow for realizing intrinsic genetic operators on Xilinx Virtex Family devices. © 2012 Elsevier B.V

Intrinsic Evolvable Hardware Platform for Digital Circuit Design and Repair Using Genetic Algorithms

A hardware/software platform for intrinsic evolvable hardware is designed and evaluated for digital circuit design and repair on Xilinx Field Programmable Gate Arrays (FPGAs). Dynamic bitstream compilation for mutation and crossover operators is achieved by directly manipulating the bitstream using a layered framework. Experimental results on a case study have shown that benchmark circuit evolution from an unseeded initial population, as well as a complete recovery of a stuck-at fault is achievable using this platform. An average of 0.47 μs is required to perform the genetic mutation, 4.2 μs to perform the single point conventional crossover, 3.1 μs to perform Partial Match Crossover (PMX) as well as Order Crossover (OX), 2.8 μs to perform Cycle Crossover (CX), and 1.1 ms for one input pattern intrinsic evaluation. These represent a performance advantage of three orders of magnitude over the JBITS software framework and more than seven orders of magnitude over the Xilinx design tool driven flow for realizing intrinsic genetic operators on Xilinx Virtex Family devices. © 2012 Elsevier B.V

Expediting Ga-Based Evolution Using Group Testing Techniques For Reconfigurable Hardware

Autonomous repair and refurbishment of reprogrammable logic devices using Genetic Algorithms can improve the fault tolerance of remote mission-critical systems. The goal of increasing availability by minimizing the repair time is addressed in this paper using a CGT-pruned Genetic Algorithm. The proposed method utilizes resource performance information obtained using Combinatorial Group Testing (CGT) techniques to evolve refurbished configurations in fewer generations than conventional genetic algorithms. A 3-bit x 2-bit Multiplier circuit was evolved using both conventional and CGT-pruned genetic algorithms. Results show that the new approach yields completely refurbished configurations 37.6% faster than conventional genetic algorithms. In addition it is demonstrated that for the same circuit, refurbishment of partially-functional configurations is a more tractable problem than designing the configurations when using genetic algorithms as results show the former to take 80% fewer generations. © 2006 IEEE

Sustainability Assurance Modeling For Sram-Based Fpga Evolutionary Self-Repair

A quantitative stochastic design technique is developed for evolvable hardware systems with self-repairing, replaceable, or amorphous spare components. The model develops a metric of sustainability which is defined in terms of residual functionality achieved from pools of amorphous spares of dynamically configurable logic elements, after repeated failure and recovery cycles. At design-time the quantity of additional resources needed to meet mission availability and lifetime requirements given the fault-susceptibility and recovery capabilities are assured within specified constraints. By applying this model to MCNC benchmark circuits mapped onto Xilinx Virtex-4 Field Programmable Gate Array (FPGA) with reconfigurable logic resources, we depict the effect of fault rates for aging-induced degradation under Time Dependent Dielectric Breakdown (TDDB) and interconnect failure under Electromigration (EM). The model considers a population-based genetic algorithm to refurbish hardware resources which realize repair policy parameters and decaying reparability as a complete case-study using published component failure rates

Sustainability Assurance Modeling For Sram-Based Fpga Evolutionary Self-Repair

A quantitative stochastic design technique is developed for evolvable hardware systems with self-repairing, replaceable, or amorphous spare components. The model develops a metric of sustainability which is defined in terms of residual functionality achieved from pools of amorphous spares of dynamically configurable logic elements, after repeated failure and recovery cycles. At design-time the quantity of additional resources needed to meet mission availability and lifetime requirements given the fault-susceptibility and recovery capabilities are assured within specified constraints. By applying this model to MCNC benchmark circuits mapped onto Xilinx Virtex-4 Field Programmable Gate Array (FPGA) with reconfigurable logic resources, we depict the effect of fault rates for aging-induced degradation under Time Dependent Dielectric Breakdown (TDDB) and interconnect failure under Electromigration (EM). The model considers a population-based genetic algorithm to refurbish hardware resources which realize repair policy parameters and decaying reparability as a complete case-study using published component failure rates

Layered Approach to Intrinsic Evolvable Hardware using Direct Bitstream Manipulation of Virtex II Pro Devices

An integrated platform for fast genetic operators is presented to support intrinsic evolution on Xilinx Virtex II Pro Field Programmable Gate Arrays (FPGAs). Dynamic bitstream compilation is achieved by directly manipulating the bitstream using a layered design. Experimental results on a case study have shown that a full design as well as a full repair is achievable using this platform with an average time of 0.4 microseconds to perform the genetic mutation, 0.7 microseconds to perform the genetic crossover, and 5.6 milliseconds for one input pattern intrinsic evaluation. This represents a performance advantage of three orders of magnitude over JBITS and more than seven orders of magnitude over the Xilinx design tool driven flow for realizing intrinsic genetic operators on a Virtex II Pro device. © 2007 IEEE

Survivability Modeling And Resource Planning For Self-Repairing Reconfigurable Device Fabrics

A resilient system design problem is formulated as the quantification of uncommitted reconfigurable resources required for a system of components to survive its lifetime within mission availability specifications. We show that this survivability metric can be calculated according to the residual functionality obtained from pools of dynamically configurable elements constituting the amorphous resource pool (ARP). The ARP is depleted based on the failure rate to replenish the functionality lost in a reconfigurable fabric due to the occurrence of permanent faults during the mission lifetime. While genetic algorithms are selected for the reparation method, any probabilistic or deterministic active repair strategy is covered without loss of generality. Parameters of this model are correlated with reliability specifications of Xilinx Virtex-4 field programmable gate array devices, which are then utilized for MCNC benchmark circuits along with a realistic space mission. Calculation of the spare fabric resources which must be budgeted for a mission, maximum mission lifetime, and repair policy parameters are realized using the proposed probabilistic survivability model for soft computing-based repair strategies

Adaptive Mitigation Of Radiation-Induced Errors And Tddb In Reconfigurable Logic Fabrics

Self-reliance capabilities of mission-critical systems gain importance as technology scaling and logic capacity of SRAM-based reconfigurable devices increase. The Sustainable Modular Adaptive Redundancy Technique (SMART) is evaluated to optimize the reliability, availability, and energy efficiency of reconfigurable logic devices with a given area footprint. A Monte Carlo driven Continuous Markov Time Chain (CMTC) simulation is conducted to assess availability using runtime adaptation with SMART in comparison to conventional design-time static Triple Modular Redundancy (TMR) techniques. In harsh environments, adaptive redundancy is shown to improve system availability under lengthy repair times, and to a more significant degree under rapid recovery times. When compared to TMR, adaptive redundancy achieves power savings ranging from 22% to 29%, at a reduced area cost ranging from 17% to 24%, while maintaining comparable levels of availability